1. Field of the Invention
The present invention relates to a non-volatile multi-state memory device using an EEPROM (Electrically Erasable Programmable ROM) and the like capable of storing multi-state data.
2. Description of the Prior Art
Alteration of a threshold level by controlling the amount of electric charge injected to a floating gate and storage of analog amounts and multi-state information have conventionally been carried out in a non-volatile memory using EEPROM or such like provided with a floating gate.
For instance, in the published translation of PCT filed patent (JP-T 04 500576) [International Laid-open No. WO 90/00801], electric charge was injected to a floating gate by supplying a high voltage write pulse to a non-volatile memory cell while sample-holding an analog signal to be inputted using an analog sample-holding circuit. Following charge injection, an analog amount corresponding to the injected charge was read out from the memory cell and compared with the sample-held analog signal and an analog amount corresponding to the input analog voltage was thus recorded in the memory cell by repeatedly supplying a write pulse until both these analog amounts match. A step-form pulse row in which voltage value increases gradually over time was used as the write pulse.
In addition, an analog sample-holding circuit of the type described above was installed respectively at each row of the memory array and while one plurality of sample-holding circuits sequentially captures the analog signals, the analog amounts held by the other plurality of sample-holding circuits was simultaneously stored in the memory cell array.
A multi-state memory is a memory for storing dispersed analog amount using a read and write configuration almost identical to that in the abovementioned publication.
In the abovementioned conventional example, since an analog signal to be inputted is held directly in an analog sample-holding circuit there are problems with data holding reliability. In addition, since data cannot be held for a long time in an analog sample-holding circuit, when input analog signals are held sequentially in a plurality of sample-holding circuits. The analog amounts held by a plurality of sample-holding circuits are simultaneously written in a plurality of memory cells after holding, only a small number of memory cells can execute writing simultaneously.
Alternatively, since the configuration is simple one in which an analog signal read from the memory cell is outputted unchanged, it is not unable to execute reading from the memory cell when attempting to transmit an analog signal to an external portion, but when the reading time for one memory cell is longer than the transmission rate to the external portion, reading cannot be completed in time.
Therefore if reading is commenced prior to transmission, the above problem is conceled. However reading of data which does not require reading is still a totally unnecessary operation and the question of at what time the reading operation should most suitably commence remains unsolved.
Furthermore, in the abovementioned conventional example, since the analog amount corresponding to an analog signal to be inputted was written in a single memory cell it was necessary to carefully control the amount of charge injected to the floating gate, requiring a memory cell with minimal variation and a complex writing circuit.
Another conventional example was disclosed in for instance the published patent (JPB 4-57294) which disclosed a non-volatile multi-state memory device wherein, in addition to latching digital data to be inputted in a data latching circuit, the multi-state storage state is read out and a sense amp is provided for outputting a digital value corresponding to this storage state. A comparator then compares this sense amp output with the data held in the data latching circuit and multi-state information is continuously written into the memory cell until the contents of both match.
However, although this configuration offers high reliability since data is held digitally by the digital latching circuit, a special sense amp is required for reading the multi-state storage state and for generating digital output and consequently circuit configuration is complex. Moreover, since digital data comparison is carried out by a comparator the scale of the circuit is inevitably large.